1. Technical Field of the Invention
The present invention relates generally to interconnect technology for routing signals through a multi-layer board, and is especially useful with flip-chip packaging.
2. Background Art
FIG. 1 illustrates, in cross-section, a motherboard coupled, such as by solder balls, to an interposer or other substrate, hereinafter referred to as a “card”. The card is coupled, such as by solder bumps, to a chip such as a flip-chip die, and illustrates one exemplary embodiment of the layers of such, according to the prior art. In the illustrated example, the card has five layers of structural material (board layers A-F), and six layers of traces or interconnects (trace layers 3F, 2F, 1FC, 1BC, 2B, and 3B), while a simplified motherboard is shown having only one structural layer (motherboard) and one trace or interconnect layer (m/b trace layer). The reader will appreciate that this is by way of example only.
Typically, the uppermost one or two interconnect layers, such as trace layer 3F and trace layer 2F, are used for routing of large numbers of input/output (I/O) signals, memory signals, clocks, strobes, voltage references, and the like (hereinafter collectively referred to as “I/O signals” for simplicity in explanation and not by way of limitation), while the lower layers are used for providing power, ground, shielding, and the like. Signals are routed between trace layers using vias. Power and ground planes may suitably be routed or coupled between adjacent layers using drilled vias. However, drilled vias may often be too large to be suitable for use in routing signals between the upper layers. In that case, one option is to use micro-vias (μvias) which may be formed by etching or the like at a much smaller scale than drilling would permit.
Please continue to make reference to FIG. 1 throughout the remainder of this patent.
FIG. 2 illustrates, in top view, an exemplary routing of such signals according to the prior art. For ease in reading FIG. 2, the general outline of the flip-chip die is shown by the dotted box 10, and an edge of the card is shown by the dashed line 5. A plurality of bumps 12 are distributed on the flip-chip die and/or the card in a pattern. Some of those bumps are for carrying I/O signals and some are for carrying power and ground signals. Typically, the I/O signals will be connected to other chips (not shown) on the motherboard; thus, it is desirable to route those signals using the generally outer bumps (such as those labeled 14 and 16) of the flip-chip die, and to use the generally inner bumps (such as those labeled 12) for power and ground.
In some high-density or high-signal-count applications, the I/O signal count and/or the I/O bump density may be such that it is difficult or impossible to route all of the I/O signals on the uppermost trace layer 3F. hi such applications, some of the I/O signals are routed on the uppermost trace layer (such as 24 and others illustrated by solid lines extending from their respective bump to the “to circuitry” indication), while other I/O signals are routed from their respective bumps down through micro-vias 17 (shown in hidden lines) to a lower trace layer such as trace layer 2F, outward to a location where the design rules and physical dimensions permit, then back up through a micro-via (such as 18) to the uppermost trace layer, and from there to their destinations. The signals which are carried below the uppermost layer are illustrated by dashed lines such as 20, and after being micro-viad back to the top layer they are illustrated by solid lines such as 22.
However, the prior art has limited ability to route large numbers of signals in high-density applications, and other limitations.